DFT (Design For Test) Engineer
Company: Etched
Location: San Jose
Posted on: April 2, 2026
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Job Description:
About Etched Etched is building the world’s first AI inference
system purpose-built for transformers - delivering over 10x higher
performance and dramatically lower cost and latency than a B200.
With Etched ASICs, you can build products that would be impossible
with GPUs, like real-time video generation models and extremely
deep & parallel chain-of-thought reasoning agents. Backed by
hundreds of millions from top-tier investors and staffed by leading
engineers, Etched is redefining the infrastructure layer for the
fastest growing industry in history. Job Summary We are seeking a
highly skilled and motivated Design For Testability (DFT) Engineer
to join our dynamic team. The ideal candidate will be responsible
for ensuring the robust testability of integrated circuits (ICs)
from the design phase through to production. This role is crucial
in improving the efficiency and effectiveness of our testing
processes, thereby enhancing overall product quality. Key
responsibilities Develop and implement robust Design for Test (DFT)
architectures for ASIC and SoC designs to enhance test coverage,
debug capability, and fault isolation. Integrate industry-standard
DFT methodologies such as scan insertion, boundary scan, Built-In
Self-Test (BIST), and Memory BIST (MBIST). Collaborate
cross-functionally with design and verification teams to ensure DFT
requirements are addressed early and consistently throughout the
design cycle. Analyze test results and silicon debug data to
provide design feedback and drive improvements in coverage, yield,
and reliability. Create and execute comprehensive DFT verification
plans to validate the correct implementation and functionality of
all DFT features. Apply simulation-based and formal verification
techniques to ensure high confidence in DFT logic correctness.
Conduct internal DFT audits and design reviews to proactively
identify and resolve gaps in testability or coverage. Support
silicon bring-up, debug, and failure analysis during post-silicon
validation to ensure successful product launch. Partner with test
engineering teams to develop and optimize Automated Test Equipment
(ATE) programs for volume production. Generate production-quality
test patterns and ensure robust failure analysis capability in
high-volume environments. Collaborate with manufacturing and
quality teams to implement data-driven test process improvements
and monitor long-term product health. Ensure test strategies are
aligned with product milestones, manufacturing timelines, and
quality/reliability targets. Author and maintain detailed
documentation for DFT architecture, test plans, procedures, and
debug guides. Share best practices through training sessions,
onboarding, and mentorship to enhance DFT awareness across design
and test teams. Stay current with emerging DFT technologies,
industry trends, and evolving standards to continually improve
internal methodologies. You may be a good fit if you have 10 years
of experience in DFT engineering with a track record of successful
test implementations for ASIC or SoC products. A deep understanding
of digital design, verification methodologies, and DFT
implementation practices. Proficiency in System Verilog and fluency
with industry-standard EDA tools (e.g., Synopsys DFT Compiler,
Cadence Encounter Test, Mentor Tessent). Scripting and automation
experience using Python, Perl, or TCL to streamline DFT
implementation and test processes. Track record of leading DFT
initiatives across multiple product generations in high-performance
or high-volume silicon environments. Strong analytical and
debugging skills, with the ability to work across teams to resolve
complex testability issues. Excellent communication and
collaboration abilities, with a focus on clarity and
cross-functional alignment. A Bachelor's degree in Electrical
Engineering, Computer Engineering, or a related field (Master’s
preferred). Strong candidates may also have experience with
Mixed-signal DFT methodologies and integration of analog
testability into SoC workflows. Industry standards such as IEEE
1149.1 (JTAG), IEEE 1500, and experience applying them in complex
designs. Yield analysis, product engineering, and contributions to
test cost reduction and quality improvement programs. Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits Housing subsidy
of $2k per month for those living within walking distance of the
office Relocation support for those moving to San Jose (Santana
Row) Various wellness benefits covering fitness, mental health, and
more Daily lunch dinner in our office How we’re different Etched
believes in the Bitter Lesson . We think most of the progress in
the AI field has come from using more FLOPs to train and run
models, and the best way to get more FLOPs is to build
model-specific hardware. Larger and larger training runs encourage
companies to consolidate around fewer model architectures, which
creates a market for single-model ASICs. We are a fully in-person
team in San Jose (Santana Row), and greatly value engineering
skills. We do not have boundaries between engineering and research,
and we expect all of our technical staff to contribute to both as
needed.
Keywords: Etched, West Sacramento , DFT (Design For Test) Engineer, Engineering , San Jose, California
